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[assembly language] CPUcoa-course-design

Description: 简单的cpu设计，包括memory，alu运算器，comp比较器以及控制器control，寄存器register等的vhdl编写的程序。-A simple cpu design, including memory, alu arithmetic logic unit, comp comparator and controller control, such as vhdl register register write programs.
Platform: | Size: 42183680 | Author: 商客 | Hits:

[VHDL-FPGA-Verilog] 3

Description: vhdl程序范例，包括测试向量，存储器举例，基本语法，状态机-vhdl program examples, including test vectors, the memory for example, basic grammar, state machine, etc.
Platform: | Size: 183296 | Author: 袁莎莎 | Hits:

[VHDL-FPGA-Verilog] VHDL_ip

Description: 基于VHDL语言的可移植通用存储器IP核的实现，本文介绍了一种利用VHDL 硬件描述语言实现可移植通用存储器IP 核的思路与方法，实验研究表明，该方法具有可移植性强、扩展性及灵活性好的特点，有效地改善了数字系统设计的效率。-VHDL language based on universal portable memory IP core implementation, this paper presents a VHDL hardware description language using a portable universal memory IP core ideas and methods, experimental studies show that the method has strong portability, scalability and flexibility and good, effective in improving the efficiency of digital system design.
Platform: | Size: 169984 | Author: lyh | Hits:

[VHDL-FPGA-Verilog] memoryarray

Description: 由VHDL撰写的两记忆体转置程序，内含testbench与转置源码。-VHDL written by the two memory migration procedures, includes testbench and migration source.
Platform: | Size: 3072 | Author: Risger | Hits:

[VHDL-FPGA-Verilog] sdram_controller_latest.tar

Description: sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.-sdram_controller_latest.tar.gz -it is memory DDR controller, but it has 8 bit only data bus wide ,and hasn’t independents clock for source read-write data and ddr + controller size. Wrote on the VHDL language.
Platform: | Size: 30720 | Author: Andrei | Hits:

[VHDL-FPGA-Verilog] ram

Description: vhdl program for random access memory and sequence detector
Platform: | Size: 1024 | Author: swap | Hits:

[VHDL-FPGA-Verilog] 2010011022

Description: 在电子领域内，频率是一种最基本的参数，并与其他许多电参量的测量方案和测量结果都有着十分密切的关系。由于频率信号抗干扰能力强、易于传输，可以获得较高的测量精度。因此，频率的测量就显得尤为重要，测频方法的研究越来越受到重视。 　　频率计作为测量仪器的一种，常称为电子计数器，它的基本功能是测量信号的频率和周期频率计的应用范围很广，它不仅应用于一般的简单仪器测量，而且还广泛应用于教学、科研、高精度仪器测量、工业控制等其它领域。在数字电路中，数字频率计属于时序电路，它主要由具有记忆功能的触发器构成。在计算机及各种数字仪表中，都得到了广泛的应用。在CMOS电路系列产品中，数字频率计时量程最大、品种很多的产品，是计算机、通讯设备、音频视频的科研生产领域不可缺少的测量仪器，并且与许多电参量的测量方案、测量结果都有十分密切的关系。因此，频率的测量就显得更为重要。 本设计设计6位十六进制频率计，以触发器和计数器为核心，由信号输入、触发、计数、数据处理和数据显示等功能模块组成。本次采用QuartusII的宏元件和VHDL语言设计两种方法来设计6位十六进制频率计，提高了测量频率的范围。 -In the electronics field, the frequency is a basic parameter, and with many other electrical parameters of the measurement program and the measurement results have a very close relationship. Since the frequency signal anti-interference ability, easy to transport, you can get higher accuracy. Therefore, the frequency of measurement is particularly important, frequency measurement method of getting attention. Frequency meter as a measuring instrument, often referred to as electronic counter, and its basic function is to measure the signal frequency and cycle frequency meter wide range of applications, it is not only used simple instruments to measure the general, but also widely used in teaching , scientific research, high-precision instrumentation, industrial control and other areas. In digital circuits, digital frequency meter are sequential circuits, it is mainly the trigger memory function by a composition. In the computer and various digital instruments, have been widely used. Prod
Platform: | Size: 611328 | Author: 程琳 | Hits:

[VHDL-FPGA-Verilog] FIFOMXN

Description: 该VHDL描述的是一个简单的先进先出存储器-a first-in first out memory, uses a synchronising clock generics allow fifos of different sizes to be instantiated
Platform: | Size: 1024 | Author: 曹影 | Hits:

[VHDL-FPGA-Verilog] my_simul

Description: s2 memory file written in vhdl
Platform: | Size: 229376 | Author: davidene | Hits:

[VHDL-FPGA-Verilog] HighSpeedFIFOsInSpartan-IIFPGAs

Description: This application note describes how to build high-speed FIFOs using the Block SelectRAM+ memory in the Spartan™ -II FPGAs. Verilog and VHDL code is available for the design. The design is for a 512x8 FIFO, but each port structure can be changed if the control logic is changed accordingly. Both a common-clock version and an independent-clock version are described.
Platform: | Size: 30720 | Author: fjmwu | Hits:

[VHDL-FPGA-Verilog] DDR1_2_WITHOUTDQ

Description: DDR1 memory code in vhdl
Platform: | Size: 7998464 | Author: yasamin | Hits:

[VHDL-FPGA-Verilog] zxcpu

Description: 用VHDL语言设计了一个含10条指令的RISC处理器。假定主存可以在一个始终周期内完成依次读写操作且和CPU同步，系统使用一个主存单元。处理器指令字长16位，包含8个通用寄存器，1个16位的指令寄存器和一个16位的程序记数器。处理器的地址总线宽度16位。数据总线宽度16位，取指和数据访问均在一跳蝻数据总线。处理器支持包含LDA，STA，MOV，MVI，ADD，SUB，AND，OR，JZ，JMP十条指令。其中仅有LDA和STA是访存指令。-VHDL language design with a RISC processor with 10 instruction. Assume that main memory can be completed in one cycle is always followed and the CPU read and write operations and the synchronization system uses a main memory unit. 16-bit instruction word processor, including 8 general purpose registers, a 16-bit instruction register and a 16-bit program counter. Processor' s address bus width 16 bits. 16-bit data bus width, fetch and data access are in the hop hoppers data bus. Processor support includes LDA, STA, MOV, MVI, ADD, SUB, AND, OR, JZ, JMP ten instructions. LDA and STA is the only one memory access instructions.
Platform: | Size: 1076224 | Author: zhaoshu | Hits:

[VHDL-FPGA-Verilog] MemManager

Description: memory manager vhdl code
Platform: | Size: 3072 | Author: SHRAVAN GARLAPATI | Hits:

[VHDL-FPGA-Verilog] an492_design_example

Description: it s a VHDL description of FLASH memory
Platform: | Size: 354304 | Author: M4RKO | Hits:

[VHDL-FPGA-Verilog] sdramtest

Description: 基于FPGA和VHDL的外部存储器读写工程，带有源代码-VHDL-based FPGA and external memory write projects with source code
Platform: | Size: 7193600 | Author: WANG | Hits:

[VHDL-FPGA-Verilog] E_Memory

Description: memory code with 64 bytes of capacity in vhdl
Platform: | Size: 1024 | Author: n | Hits:

[VHDL-FPGA-Verilog] mon

Description: vhdl code for memory core
Platform: | Size: 1024 | Author: JP | Hits:

[VHDL-FPGA-Verilog] cpu-and-ram

Description: 这是一个用VHDL语言写的简单带存储器的CPU设计，不涉及流水线设计，只是简单的利用QUARTUES II里的ram-This is a simple memory write VHDL CPU design, does not involve the assembly line design, simply use the ram in QUARTUES II
Platform: | Size: 1262592 | Author: 郭雅娟 | Hits:

[VHDL-FPGA-Verilog] the-strong-cpu-design

Description: 增强型CPU设计，带有PC指针与存储器，用VHDL语言写的，不含流水线设计，实现二进制灯循环亮-Enhanced CPU design, with the PC pointer memory write VHDL language, non-pipelined design to achieve binary bright light cycle
Platform: | Size: 1609728 | Author: 郭雅娟 | Hits:

[VHDL-FPGA-Verilog] Package

Description: Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation-Package consists of two pdf files: i)cdr project: theory and implementation of vhdl ii)I2C bus controller: xilinx implementation of uC interface on CPLD Package consists of 7 vhdl files: string_detector: detects the continuous string of 111 led_driver: code for running leds on dvpt board clk_div: clock divider circuitry (component for led code) mem: memory component for led code ram_dual: dual port ram implementation
Platform: | Size: 4604928 | Author: Sharav | Hits:
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